A new type of SRAM device using Negative Differential Resistance Field Effect Transistors (NDR FETs) is described in detail in a patent application Ser. No. 10/029,077 filed Dec. 21, 2001 by T.-J. King and assigned to the present assignee, and published on May 9, 2002 as Publication No. 2002/0054502. The NDR FET structure, operation and method of making the same are discussed in detail in patent application Ser. No. 09/603,101 filed Jun. 22, 2000 by King et al., which is also assigned to the present assignee. Such details are also disclosed in a corresponding PCT application PCT/US01/19825 which was published as publication no. WO 01/99153 on Dec. 27, 2001. Methods for reducing soft error rates in such NDR FET based SRAM cells are described in U.S. Pat. No. 6,567,292, entitled “NEGATIVE DIFFERENTIAL RESISTANCE (NDR) ELEMENT AND MEMORY WITH REDUCED SOFT ERROR RATE” by King, and issued on May 20, 2003. The above materials are hereby incorporated by reference.
As is well-known in the art, some of the important benchmarks for memory devices that determine the suitability for a particular application include the quiescent power rating, read speed and write speed. Furthermore, the peak-to-valley ratio (PVR) of the operating and quiescent current for a cell is also a significant factor that limits the feasibility of certain embodiments. For many applications it is believed that a PVR must exceed 10,000 to be practical at commercially desirable densities (i.e., in the MB range and above). Thus, it is apparent that the aforementioned NDR based SRAMs (and other NDR based memories) would also benefit from an increase in operating performance of the NDR elements to meet the aforementioned benchmarks.